1. Field
Various exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device.
2. Description of the Related Art
System in package (SIP) technique, by which a controller and a memory device is packaged in a single package, was introduced as the performance and the speed of a semiconductor memory device increase. Since there is a limit in increasing the input/output speed of single data in the semiconductor memory device, the number of input/output pins is expanded to increase the overall bandwidth thereof. A high bandwidth memory (HBM) device processes a large amount of data at a high speed through the expanded number of input/output pins.
The HBM may have 8 channels, each of which has 128 input/output pins and operates independently. Also, the HBM comprises a base die and a core die. The core die includes a lot of memory cells and the base die performs data communication with a controller.
The HBM, unlike a general double data rate (DDR) dynamic random access memory device, does not have a separated command pin and receives a command signal through some of the address pins. An address of the HBM is classified into a row address RA and a column address CA, and has 0.5 tCK of a valid data window tDV as a double data rate (DDR) instead of 1 tCK of the valid data window tDV as a single data rate (SDR). These particular structures of HBM reduce the number of address pins by replacing the command pin with the address pin and by processing the addresses at the double data rate. Also, the classification of the row address and the column address gets both of the row address and the column address simultaneously processed for fast access to the semiconductor memory device.
For testing the HBM, all of the row addresses and the column addresses may be set, and a tester for the HBM may input commands and addresses to the HBM within 1 tCK. A row command and a column command are inputted within 1 tCK. However, an active command among the row commands may be inputted through 2 tCK since there are lots of row addresses corresponding to the active command.
For this reason, the typical HBM has 2 row address pins for a rising address and a falling address, respectively, and the tester for the HBM inputs the active command through the 2 row address pins within 2 tCK.
During the input of the active command, the column address pins of the HBM are not used.
Therefore, there are needs for reducing the number of row address pins assigned to the input of the active command, and using column address pins for the input of the active command.